/**************************************
* Module: v1
* Date:2013-07-11  
* Author: leon     
*
* Description: 
***************************************/
module  v1(
);
wire [3:0] A_BUS,Z_BUS;
wire [0:3] B_BUS;

assign Z_BUS=A_BUS;
assign B_BUS=A_BUS;

endmodule