module mux4alt_tb
();
wire A,B,C,D;
reg [3:0] compactar;
reg [1:0] sel;
wire sal;
mux4a1t uut (.A(A),.B(B),.C(C),.D(D),.sel(sel),.sal(sal));
assign {A,B,C,D}=compactar;
initial begin: TB
integer i,j;
$dumpfile("test.vcd");
$dumpvars(0,mux4alt_tb);
for(i=0;i<=15;i=i+1) begin
compactar=i;
for(j=0;j<=3;j=j+1) begin
sel=j;
#10
$write ("Entrada %b sel %d sal %b \n",compactar,sel,sal);
if (compactar[j]!=sal) $write("HORROR/ERROR\n");
end
end
end
endmodule
This page: |
Created: | Tue Oct 1 11:42:01 2013 |
|
From: |
../mux4a1t_tb.v |