Hierarchy | Files | Modules | Signals | Tasks | Functions | Help |
module decn
(ent,sal); parameter ANCHO=4; input [ANCHO-1:0] ent; output reg [(1<<ANCHO)-1:0] sal; always @ (ent)begin sal=0; sal[ent]=1'b1; end endmodule
Hierarchy | Files | Modules | Signals | Tasks | Functions | Help |
This page: | Created: | Tue Oct 1 11:42:01 2013 |
From: | ../decn.v |
Verilog converted to html by v2html 7.30.1.3 (written by Costas Calamvokis). | Help |