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[Up: mux4alt_tb uut]
module mux4a1tIndex (A,B,C,D,sel,sal);
input A,B,C,D;
output sal;
input [1:0] sel;
wire [3:0] sallineal;
wire [3:0] compactar;

dec2x4 uut (.ent(sel),.sal(sallineal));
assign compactar={A,B,C,D};
generate
  for (i=0;i<=3;i=i+1) begin: uno
    assign sal = sallineal[i] ? compactar[i]: 1'bz;
  end
endgenerate
endmodule
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This page: Created:Tue Oct 1 11:42:01 2013
From: ../mux4a1t.v

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