HierarchyFilesModulesSignalsTasksFunctionsHelp
module decn_tbIndex ();

reg [5:0] ent;
wire [63:0] sal;

decngray #(6) UUT (.ent(ent),
	.sal(sal));
initial begin: TB
	integer i,j;
	$dumpfile("test.vcd");
$dumpvars(0,decn_tb);
	for (i=0;i<=63;i=i+1) begin
          ent=i;
           #10;
	   $write ("Tiempo: %d  entra %d y sale %b \n",$time,ent,sal);
           end
  end
endmodule
		

HierarchyFilesModulesSignalsTasksFunctionsHelp

This page: Created:Tue Oct 1 10:29:07 2013
From: ../decngray_tb.v

Verilog converted to html by v2html 7.30.1.3 (written by Costas Calamvokis).Help