v2 Project Status (09/23/2013 - 16:06:30)
Project File: prueba.xise Parser Errors: No Errors
Module Name: v2 Implementation State: Programming File Not Generated
Target Device: xc4vlx160-10ff1148
  • Errors:
  
Product Version:ISE 12.2
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment:  
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentvie sep 20 16:32:05 2013   
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Datevie sep 20 17:30:36 2013
WebTalk ReportCurrentlun sep 23 16:06:29 2013
WebTalk Log FileCurrentlun sep 23 16:06:30 2013

Date Generated: 09/23/2013 - 16:06:30