Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:12.2 (ISE) - M.63c Target Family: Virtex4
OS Platform: LIN Target Device: xc4vlx160
Project ID (random number) 218cd7acf0974e52b84496371e20201d.A1459B3F470A7752B465B909766142AA.1 Target Package: ff1148
Registration ID 174111436_174111437_174416250 Target Speed: -10
Date Generated 2013-09-23T16:06:29 Tool Flow ISE
 
User Environment
OS Name Gentoo OS Release NAME=Gentoo
CPU Name Intel(R) Core(TM)2 Duo CPU E8600 @ 3.33GHz CPU Speed 3333.000 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=6
  • AGG_IO=6
  • AGG_SLICE=2
  • NUM_4_INPUT_LUT=4
  • NUM_BONDED_IOB=6
  • NUM_SLICEL=2
 		NetStatistics
  • NumNets_Active=25
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=24
  • NumNodesOfType_Active_DOUBLE=22
  • NumNodesOfType_Active_INPUT=8
  • NumNodesOfType_Active_IOBIN2OUT=2
  • NumNodesOfType_Active_IOBINPUT=4
  • NumNodesOfType_Active_IOBOUTPUT=6
  • NumNodesOfType_Active_OMUX=8
  • NumNodesOfType_Active_OUTBOUND=7
  • NumNodesOfType_Active_OUTPUT=17
  • NumNodesOfType_Active_PADINPUT=4
  • NumNodesOfType_Active_PADOUTPUT=2
  • NumNodesOfType_Active_PINFEED=50
  • NumNodesOfType_Active_UNUSED=1
  • NumNodesOfType_Active_VLONG=6
  • NumNodesOfType_Active_VUNIHEX=4
  • NumNodesOfType_Gnd_BOUNCEIN=3
  • NumNodesOfType_Gnd_HGNDOUT=1
  • NumNodesOfType_Gnd_INPUT=6
  • NumNodesOfType_Gnd_PINFEED=6
  • NumNodesOfType_Vcc_HVCCOUT=12
  • NumNodesOfType_Vcc_INPUT=25
  • NumNodesOfType_Vcc_KVCCOUT=13
  • NumNodesOfType_Vcc_PINFEED=25
 SiteStatistics
  • IOB-LOWCAPIOB=6
  • SLICEL-SLICEM=1
 		SiteSummary
  • DCM_ADV=12
  • DCM_ADV_DCM_ADV=12
  • IOB=6
  • IOB_INBUF=2
  • IOB_OUTBUF=4
  • IOB_PAD=6
  • PMV=1
  • PMV_PMV=1
  • SLICEL=2
  • SLICEL_F=2
  • SLICEL_G=2
 
Configuration Data
DCM_ADV
  • CTLMODE=[CTLMODE:12] [CTLMODE_INV:0]
  • PSEN=[PSEN_INV:12] [PSEN:0]
 DCM_ADV_DCM_ADV
  • BGM_CONFIG_REF_SEL=[CLKIN:12]
  • BGM_DIVIDE=[16:12]
  • BGM_LDLY=[5:12]
  • BGM_MODE=[BG_SNAPSHOT:12]
  • BGM_MULTIPLY=[16:12]
  • BGM_SAMPLE_LEN=[2:12]
  • BGM_SDLY=[3:12]
  • BGM_VADJ=[5:12]
  • BGM_VLDLY=[7:12]
  • BGM_VSDLY=[0:12]
  • CLKDV_DIVIDE=[2.0:12]
  • CLKFX_DIVIDE=[1:12]
  • CLKFX_MULTIPLY=[4:12]
  • CLKIN_DIVIDE_BY_2=[TRUE:12]
  • CLKOUT_PHASE_SHIFT=[FIXED:12]
  • CLK_FEEDBACK=[1X:12]
  • CTLMODE=[CTLMODE:12] [CTLMODE_INV:0]
  • DCM_CLKDV_CLKFX_ALIGNMENT=[TRUE:12]
  • DCM_EXT_FB_EN=[FALSE:12]
  • DCM_LOCK_HIGH=[FALSE:12]
  • DCM_PERFORMANCE_MODE=[MAX_SPEED:12]
  • DCM_UNUSED_TAPS_POWERDOWN=[FALSE:12]
  • DCM_VREF_SOURCE=[VBG_DLL:12]
  • DCM_VREG_ENABLE=[FALSE:12]
  • DESKEW_ADJUST=[20:12]
  • DFS_AVE_FREQ_ADJ_INTERVAL=[3:12]
  • DFS_AVE_FREQ_GAIN=[2.0:12]
  • DFS_AVE_FREQ_SAMPLE_INTERVAL=[2:12]
  • DFS_COARSE_SEL=[LEGACY:12]
  • DFS_EARLY_LOCK=[FALSE:12]
  • DFS_EN_RELRST=[TRUE:12]
  • DFS_EXTEND_FLUSH_TIME=[FALSE:12]
  • DFS_EXTEND_HALT_TIME=[FALSE:12]
  • DFS_EXTEND_RUN_TIME=[FALSE:12]
  • DFS_FINE_SEL=[LEGACY:12]
  • DFS_FREQUENCY_MODE=[LOW:12]
  • DFS_NON_STOP=[FALSE:12]
  • DFS_OSCILLATOR_MODE=[PHASE_FREQ_LOCK:12]
  • DFS_SKIP_FINE=[FALSE:12]
  • DFS_TP_SEL=[LEVEL:12]
  • DFS_TRACKMODE=[1:12]
  • DLL_CONTROL_CLOCK_SPEED=[HALF:12]
  • DLL_CTL_SEL_CLKIN_DIV2=[FALSE:12]
  • DLL_DESKEW_LOCK_BY1=[FALSE:12]
  • DLL_FREQUENCY_MODE=[LOW:12]
  • DLL_PD_DLY_SEL=[0:12]
  • DLL_PERIOD_LOCK_BY1=[FALSE:12]
  • DLL_PHASE_DETECTOR_AUTO_RESET=[TRUE:12]
  • DLL_PHASE_DETECTOR_MODE=[ENHANCED:12]
  • DLL_PHASE_SHIFT_CALIBRATION=[AUTO_DPS:12]
  • DLL_PHASE_SHIFT_LOCK_BY1=[FALSE:12]
  • DUTY_CYCLE_CORRECTION=[TRUE:12]
  • PMCD_SYNC=[FALSE:12]
  • PSEN=[PSEN_INV:12] [PSEN:0]
  • STARTUP_WAIT=[FALSE:12]
 IOB_PAD
  • DRIVEATTRBOX=[12:4]
  • IOATTRBOX=[LVCMOS25:6]
  • SLEW=[SLOW:4]
 
Pin Data
DCM_ADV
  • CLK0=12
  • CLKFB=12
  • CLKIN=12
  • CTLMODE=12
  • PSEN=12
 DCM_ADV_DCM_ADV
  • CLK0=12
  • CLKFB=12
  • CLKIN=12
  • CTLMODE=12
  • PSEN=12
 IOB
  • I=2
  • O=4
  • PAD=6
 IOB_INBUF
  • OUT=2
  • PAD=2
 IOB_OUTBUF
  • IN=4
  • OUT=4
 IOB_PAD
  • PAD=6
 PMV
  • A0=1
  • A1=1
  • A2=1
  • A3=1
  • A4=1
  • A5=1
  • EN=1
  • ODIV4=1
 PMV_PMV
  • A0=1
  • A1=1
  • A2=1
  • A3=1
  • A4=1
  • A5=1
  • EN=1
  • ODIV4=1
 SLICEL
  • F1=2
  • F2=2
  • G1=2
  • G2=2
  • X=2
  • Y=2
 SLICEL_F
  • A1=2
  • A2=2
  • D=2
 SLICEL_G
  • A1=2
  • A2=2
  • D=2
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc4vlx160-ff1148-10 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc4vlx160-ff1148-10 -global_opt off -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 10 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
_impact 7 5 0 0 0 0 0
bitgen 7 7 0 0 0 0 0
edif2ngd 43 43 0 0 0 0 0
map 115 111 0 0 0 0 0
netgen 33 33 0 0 0 0 0
ngc2edif 2 2 0 0 0 0 0
ngcbuild 34 34 0 0 0 0 0
ngdbuild 124 121 0 0 0 0 0
obngc 29 29 0 0 0 0 0
par 108 105 0 0 0 0 0
trce 102 102 0 0 0 0 0
xpwr 1 1 0 0 0 0 0
xst 446 402 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/ite_c_overview.htm ( 2 ) /doc/usenglish/isehelp/pn_db_adding_source_files.htm ( 1 )
/doc/usenglish/isehelp/pn_db_nsw_select_ip.htm ( 1 ) /doc/usenglish/isehelp/xpa_c_filetypes.htm ( 1 )
/doc/usenglish/isehelp/xpa_c_overview.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/v2_tb PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Constraints Editor
PROP_intProjectCreationTimestamp=2013-09-20T16:30:03 PROP_intWbtProjectID=A1459B3F470A7752B465B909766142AA
PROP_intWbtProjectIteration=1 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_selectedSimRootSourceNode_behav=work.v2_tb
PROP_AutoTop=false PROP_CompxlibEdkSimLib=false
PROP_DevFamily=Virtex4 PROP_DevDevice=xc4vlx160
PROP_DevFamilyPMName=virtex4 PROP_DevPackage=ff1148
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-10
PROP_PreferredLanguage=Verilog FILE_VERILOG=5
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_LUT2=4 NGDBUILD_NUM_OBUF=4
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_LUT2=4 NGDBUILD_NUM_OBUF=4
 
ISim Statistics
Xilinx HDL Libraries Used=
Fuse Resource Usage=120 ms, 66444 KB