ISim log file
Running: /home/leon/Dc2014/Verilog/sourceverilog/simples/prueba/v2_tb_isim_beh.exe -gui -tclbatch isim.cmd -wdb /home/leon/Dc2014/Verilog/sourceverilog/simples/prueba/v2_tb_isim_beh.wdb 
ISim M.63c (signature 0x2f7eec00)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.


----------------------------------------------------------------------
This is a Full version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Tiempo:                   10   0 0  0 
Tiempo:                   20   1 1  X 
Tiempo:                   30   2 0  X 
Tiempo:                   40   3 1  X 
Tiempo:                   50   4 0  X 
Tiempo:                   60   5 1  5 
Tiempo:                   70   6 0  X 
Tiempo:                   80   7 1  X 
Tiempo:                   90   8 0  8 
Tiempo:                  100   9 1  X 
Tiempo:                  110  10 0  X 
Tiempo:                  120  11 1  X 
Tiempo:                  130  12 0  X 
Tiempo:                  140  13 1 13 
Tiempo:                  150  14 0  X 
Tiempo:                  160  15 1  X