Running: /share/Xilinx/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o /home/leon/Dc2014/Verilog/sourceverilog/simples/prueba/v2_tb_isim_beh.exe -prj /home/leon/Dc2014/Verilog/sourceverilog/simples/prueba/v2_tb_beh.prj work.v2_tb work.glbl 
ISim M.63c (signature 0x2f7eec00)
Number of CPUs detected in this system: 2
Turning on mult-threading, number of parallel sub-compilation jobs: 4 
Determining compilation order of HDL files
Analyzing Verilog file \"/home/leon/Dc2014/Verilog/sourceverilog/simples/prueba/v2.v\" into library work
Analyzing Verilog file \"/home/leon/Dc2014/Verilog/sourceverilog/simples/prueba/../v2_tb.v\" into library work
Analyzing Verilog file \"/share/Xilinx/ISE_DS/ISE//verilog/src/glbl.v\" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 27504 KB
Fuse CPU Usage: 110 ms
Compiling module v2
Compiling module v2_tb
Compiling module glbl
Time Resolution for simulation is 1ps.
Waiting for 2 sub-compilation(s) to finish...
Compiled 3 Verilog Units
Built simulation executable /home/leon/Dc2014/Verilog/sourceverilog/simples/prueba/v2_tb_isim_beh.exe
Fuse Memory Usage: 66444 KB
Fuse CPU Usage: 120 ms
GCC CPU Usage: 230 ms