v2 Project Status (09/23/2013 - 16:06:30)
Project File: prueba.xise Parser Errors: No Errors
Module Name: dec2x4b Implementation State: Programming File Generated
Target Device: xc4vlx160-10ff1148
  • Errors:
 No Errors
Product Version:ISE 12.2
  • Warnings:
 No Warnings
Design Goal: Balanced
  • Routing Results:
 All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
 0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of 4 input LUTs 4 135,168 1%  
Number of occupied Slices 2 67,584 1%  
    Number of Slices containing only related logic 2 2 100%  
    Number of Slices containing unrelated logic 0 2 0%  
Total Number of 4 input LUTs 4 135,168 1%  
Number of bonded IOBs 6 768 1%  
Average Fanout of Non-Clock Nets 1.89      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentlun sep 23 16:04:54 2013000
Translation ReportCurrentlun sep 23 16:04:58 2013000
Map ReportCurrentlun sep 23 16:05:07 2013003 Infos (3 new)
Place and Route ReportCurrentlun sep 23 16:05:41 2013001 Info (1 new)
Power Report     
Post-PAR Static Timing ReportCurrentlun sep 23 16:05:54 2013003 Infos (3 new)
Bitgen ReportCurrentlun sep 23 16:06:27 2013001 Info (1 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Datevie sep 20 17:30:36 2013
WebTalk ReportCurrentlun sep 23 16:06:29 2013
WebTalk Log FileCurrentlun sep 23 16:06:30 2013

Date Generated: 09/23/2013 - 16:06:30