Release 12.2 Map M.63c (lin) Xilinx Mapping Report File for Design 'dec2x4b' Design Information ------------------ Command Line : map -intstyle ise -p xc4vlx160-ff1148-10 -global_opt off -cm area -ir off -pr off -c 100 -o dec2x4b_map.ncd dec2x4b.ngd dec2x4b.pcf Target Device : xc4vlx160 Target Package : ff1148 Target Speed : -10 Mapper Version : virtex4 -- $Revision: 1.52 $ Mapped Date : Mon Sep 23 16:05:00 2013 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of 4 input LUTs: 4 out of 135,168 1% Logic Distribution: Number of occupied Slices: 2 out of 67,584 1% Number of Slices containing only related logic: 2 out of 2 100% Number of Slices containing unrelated logic: 0 out of 2 0% *See NOTES below for an explanation of the effects of unrelated logic. Total Number of 4 input LUTs: 4 out of 135,168 1% The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. Number of bonded IOBs: 6 out of 768 1% Average Fanout of Non-Clock Nets: 1.89 Peak Memory Usage: 349 MB Total REAL time to MAP completion: 7 secs Total CPU time to MAP completion: 4 secs NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group and Partition Summary Section 10 - Timing Report Section 11 - Configuration String Information Section 12 - Control Set Information Section 13 - Utilization by Hierarchy Section 1 - Errors ------------------ Section 2 - Warnings -------------------- WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. Section 3 - Informational ------------------------- INFO:Security:56 - Part 'xc4vlx160' is not a WebPack part. INFO:MapLib:562 - No environment variables are currently set. INFO:MapLib:797 - Your design is targeting LX/SX Production Step 0/1/ES devices. Please note that there are new specifications for the DCMs to guarantee maximum frequency performance. If the DCM input clock might stop or if the DCM reset might be asserted for an extended time, then use of the dcm_standby macro may be required. Please see Answer Record 21127. INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. Section 4 - Removed Logic Summary --------------------------------- Section 5 - Removed Logic ------------------------- Section 6 - IOB Properties -------------------------- +---------------------------------------------------------------------------------------------------------------------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | | | | | | Term | Strength | Rate | | | Delay | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ | ent<0> | IOB | INPUT | LVCMOS25 | | | | | | | | ent<1> | IOB | INPUT | LVCMOS25 | | | | | | | | sal<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | sal<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | sal<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | sal<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ Section 7 - RPMs ---------------- Section 8 - Guide Report ------------------------ Guide not run on this design. Section 9 - Area Group and Partition Summary -------------------------------------------- Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Area Group Information ---------------------- No area groups were found in this design. ---------------------- Section 10 - Timing Report -------------------------- This design was not run using timing mode. Section 11 - Configuration String Details ----------------------------------------- Use the "-detail" map option to print out Configuration Strings Section 12 - Control Set Information ------------------------------------ No control set information for this architecture. Section 13 - Utilization by Hierarchy ------------------------------------- Use the "-detail" map option to print out the Utilization by Hierarchy section.