Release 12.2 par M.63c (lin) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. harmachis.act:: Mon Sep 23 16:05:09 2013 par -w -intstyle ise -ol high -t 1 dec2x4b_map.ncd dec2x4b.ncd dec2x4b.pcf Constraints file: dec2x4b.pcf. Loading device for application Rf_Device from file '4vlx160.nph' in environment /share/Xilinx/ISE_DS/ISE/. "dec2x4b" is an NCD, version 3.2, device xc4vlx160, package ff1148, speed -10 This design is using the default stepping level (major silicon revision) for this device (1). Unless your design is targeted at devices of this stepping level, it is recommended that you explicitly specify the stepping level of the parts you will be using. This will allow the tools to take advantage of any available performance and functional enhancements for this device. The latest stepping level for this device is '2'. Additional information on "stepping level" is available at support.xilinx.com. vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv INFO:Security:56 - Part 'xc4vlx160' is not a WebPack part. WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. ---------------------------------------------------------------------- Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". Device speed data version: "PRODUCTION 1.69 2010-06-22". Device Utilization Summary: Number of External IOBs 6 out of 768 1% Number of LOCed IOBs 0 out of 6 0% Number of Slices 2 out of 67584 1% Number of SLICEMs 0 out of 33792 0% Overall effort level (-ol): High Placer effort level (-pl): High Placer cost table entry (-t): 1 Router effort level (-rl): High Starting initial Timing Analysis. REAL time: 12 secs Finished initial Timing Analysis. REAL time: 12 secs Starting Placer Total REAL time at the beginning of Placer: 13 secs Total CPU time at the beginning of Placer: 12 secs Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis (Checksum:d7) REAL time: 14 secs Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check (Checksum:d7) REAL time: 14 secs Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization (Checksum:44f7f607) REAL time: 14 secs Phase 4.2 Initial Clock and IO Placement ... Phase 4.2 Initial Clock and IO Placement (Checksum:a22e0451) REAL time: 14 secs Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization (Checksum:a22e0451) REAL time: 14 secs Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment (Checksum:a22e0451) REAL time: 14 secs Phase 7.3 Local Placement Optimization ... Phase 7.3 Local Placement Optimization (Checksum:119781a3) REAL time: 14 secs Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization (Checksum:119781a3) REAL time: 14 secs Phase 9.8 Global Placement .. Phase 9.8 Global Placement (Checksum:7d19da38) REAL time: 15 secs Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization (Checksum:7d19da38) REAL time: 15 secs Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization (Checksum:7d19da38) REAL time: 15 secs Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization (Checksum:7d19da38) REAL time: 15 secs Phase 13.34 Placement Validation Phase 13.34 Placement Validation (Checksum:7d19da38) REAL time: 15 secs Total REAL time to Placer completion: 15 secs Total CPU time to Placer completion: 13 secs Writing design to file dec2x4b.ncd Starting Router Phase 1 : 67 unrouted; REAL time: 17 secs Phase 2 : 24 unrouted; REAL time: 17 secs Phase 3 : 0 unrouted; REAL time: 17 secs Phase 4 : 0 unrouted; (Par is working to improve performance) REAL time: 27 secs Updating file: dec2x4b.ncd with current fully routed design. Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 27 secs Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 27 secs Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 27 secs Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 27 secs Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 27 secs Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 27 secs Total REAL time to Router completion: 27 secs Total CPU time to Router completion: 26 secs Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Generating "PAR" statistics. Timing Score: 0 (Setup: 0, Hold: 0) Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 32 secs Total CPU time to PAR completion: 30 secs Peak Memory Usage: 421 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 0 Number of info messages: 1 Writing design to file dec2x4b.ncd PAR done!