//`timescale 10ns/1ns
module ine_tb ();

reg ent;
wire  sal;
ine UUT (ent,sal);
initial begin: TB
	integer i;
$dumpfile("test.vcd");
$dumpvars(0,ine_tb);

	ent=0;
	 $write ("Tiempo: %d  %d %d \n",$time, ent,sal);
	#10;
 $write ("Tiempo: %d  %d %d \n",$time, ent,sal);
	ent=1;
     	 $write ("Tiempo: %d  %d %d \n",$time, ent,sal);
	for (i=1;i<100;i=i+1) begin
	#10;
	  $write ("Tiempo: %d  %d %d \n",$time, ent,sal);
	end
	
  end
endmodule