#-----------------------------------------------------------
# Vivado v2015.2 (64-bit)
# SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
# IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
# Start of session at: Tue Oct 20 08:32:33 2015
# Process ID: 11501
# Log file: /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado.log
# Journal file: /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/share2/Xilinx/Vivado/2015.2/data/ip'.
open_project: Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 5727.348 ; gain = 90.414 ; free physical = 110 ; free virtual = 8278
file mkdir /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/new
close [ open /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/new/alarma.v w ]
add_files /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/new/alarma.v
update_compile_order -fileset sources_1
reset_run synth_1
launch_runs synth_1
INFO: [HDL 9-2216] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/new/alarma.v" into library work [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/new/alarma.v:1]
INFO: [HDL 9-2216] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" into library work [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v:1]
[Tue Oct 20 09:02:10 2015] Launched synth_1...
Run output will be captured here: /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.runs/synth_1/runme.log
launch_runs impl_1
[Tue Oct 20 09:02:54 2015] Launched impl_1...
Run output will be captured here: /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.runs/impl_1/runme.log
open_run impl_1
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2015.2
INFO: [Device 21-403] Loading part xc7vx485tffg1157-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00,04 ; elapsed = 00:00:00,09 . Memory (MB): peak = 6085.363 ; gain = 1.000 ; free physical = 762 ; free virtual = 7622
Restored from archive | CPU: 0,040000 secs | Memory: 0,038612 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00,04 ; elapsed = 00:00:00,09 . Memory (MB): peak = 6085.363 ; gain = 1.000 ; free physical = 762 ; free virtual = 7622
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

open_run: Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 6231.594 ; gain = 450.133 ; free physical = 515 ; free virtual = 7451
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
exit
INFO: [Common 17-206] Exiting Vivado at Tue Oct 20 09:48:01 2015...