#-----------------------------------------------------------
# Vivado v2015.2 (64-bit)
# SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
# IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
# Start of session at: Mon Oct 19 16:53:31 2015
# Process ID: 1284
# Log file: /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado.log
# Journal file: /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado.jou
#-----------------------------------------------------------
start_gui
create_project project_1 /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1 -part xc7vx485tffg1157-1
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/share2/Xilinx/Vivado/2015.2/data/ip'.
create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:22 . Memory (MB): peak = 5717.223 ; gain = 35.078 ; free physical = 32 ; free virtual = 7831
import_files -norecurse /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/conta99.v
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
set_property SOURCE_SET sources_1 [get_filesets sim_1]
import_files -fileset sim_1 -norecurse /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/conta99.v
file mkdir /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sim_1/new
set_property SOURCE_SET sources_1 [get_filesets sim_1]
close [ open /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sim_1/new/cont99_tb.v w ]
add_files -fileset sim_1 /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sim_1/new/cont99_tb.v
update_compile_order -fileset sim_1
remove_files -fileset sim_1 /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sim_1/imports/examen/conta99.v
update_compile_order -fileset sim_1
update_compile_order -fileset sim_1
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'cont99_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav'
xvlog -m64 --relax -prj cont99_tb_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bcd1contador
ERROR: [VRFC 10-91] ckj is not declared [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v:8]
ERROR: [VRFC 10-1040] module bcd1contador ignored due to previous errors [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v:1]
INFO: [VRFC 10-311] analyzing module cont99
ERROR: [VRFC 10-91] salida is not declared [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v:24]
ERROR: [VRFC 10-1241] port cuenta is not defined [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v:26]
ERROR: [VRFC 10-1040] module cont99 ignored due to previous errors [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v:24]
INFO: [USF-XSim-99] Step results log file:'/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav/xvlog.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav/xvlog.log' file for more information.
launch_runs synth_1
INFO: [HDL 9-2216] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" into library work [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v:1]
[Mon Oct 19 18:05:01 2015] Launched synth_1...
Run output will be captured here: /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.runs/synth_1/runme.log
reset_run synth_1
launch_runs synth_1
INFO: [HDL 9-2216] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" into library work [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v:1]
[Mon Oct 19 18:06:22 2015] Launched synth_1...
Run output will be captured here: /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.runs/synth_1/runme.log
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'cont99_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav'
xvlog -m64 --relax -prj cont99_tb_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bcd1contador
INFO: [VRFC 10-311] analyzing module cont99
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sim_1/new/cont99_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module cont99_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav'
Vivado Simulator 2015.2
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: /share2/Xilinx/Vivado/2015.2/bin/unwrapped/lnx64.o/xelab -wto c7af4f02b1ba478697011b7527df2967 --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot cont99_tb_behav xil_defaultlib.cont99_tb xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
WARNING: [VRFC 10-426] cannot find port salida on this module [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sim_1/new/cont99_tb.v:27]
WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port ce [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v:30]
Completed static elaboration
Starting simulation data flow analysis
ERROR: [XSIM 43-3250] File /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v, line 25. Unsupported named port connection association : .salida(sal) where formal is alias port.
INFO: [USF-XSim-99] Step results log file:'/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav/elaborate.log' file for more information.
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'cont99_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav'
xvlog -m64 --relax -prj cont99_tb_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bcd1contador
INFO: [VRFC 10-311] analyzing module cont99
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sim_1/new/cont99_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module cont99_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav'
Vivado Simulator 2015.2
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: /share2/Xilinx/Vivado/2015.2/bin/unwrapped/lnx64.o/xelab -wto c7af4f02b1ba478697011b7527df2967 --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot cont99_tb_behav xil_defaultlib.cont99_tb xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port ce [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v:30]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 25. Module cont99 doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 1. Module bcd1contador doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 1. Module bcd1contador doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 25. Module cont99 doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 1. Module bcd1contador doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 1. Module bcd1contador doesn't have a timescale but at least one module in design has a timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
WARNING: [XSIM 43-3447] Restricting number of parallel compilation jobs to 4 to avoid system resource limitations.
Compiling module xil_defaultlib.bcd1contador
Compiling module xil_defaultlib.cont99
Compiling module xil_defaultlib.cont99_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot cont99_tb_behav
run_program: Time (s): cpu = 00:00:00,52 ; elapsed = 00:00:06 . Memory (MB): peak = 5794.289 ; gain = 0.000 ; free physical = 395 ; free virtual = 7882
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "cont99_tb_behav -key {Behavioral:sim_1:Functional:cont99_tb} -tclbatch {cont99_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.2
Time resolution is 1 ps
source cont99_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
xsim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 5825.789 ; gain = 31.500 ; free physical = 330 ; free virtual = 7874
INFO: [USF-XSim-96] XSim completed. Design snapshot 'cont99_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:15 . Memory (MB): peak = 5825.789 ; gain = 31.500 ; free physical = 330 ; free virtual = 7874
run all
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
run: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 5835.176 ; gain = 9.387 ; free physical = 35 ; free virtual = 7855
INFO: [Common 17-344] 'run' was cancelled
restart
INFO: [Simtcl 6-17] Simulation restarted
run all
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
run: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 5835.176 ; gain = 0.000 ; free physical = 32 ; free virtual = 7826
INFO: [Common 17-344] 'run' was cancelled
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'cont99_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav'
xvlog -m64 --relax -prj cont99_tb_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bcd1contador
INFO: [VRFC 10-311] analyzing module cont99
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sim_1/new/cont99_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module cont99_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav'
Vivado Simulator 2015.2
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: /share2/Xilinx/Vivado/2015.2/bin/unwrapped/lnx64.o/xelab -wto c7af4f02b1ba478697011b7527df2967 --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot cont99_tb_behav xil_defaultlib.cont99_tb xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port ce [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v:32]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 27. Module cont99 doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 1. Module bcd1contador doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 1. Module bcd1contador doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 27. Module cont99 doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 1. Module bcd1contador doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 1. Module bcd1contador doesn't have a timescale but at least one module in design has a timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
WARNING: [XSIM 43-3447] Restricting number of parallel compilation jobs to 4 to avoid system resource limitations.
Compiling module xil_defaultlib.bcd1contador
Compiling module xil_defaultlib.cont99
Compiling module xil_defaultlib.cont99_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot cont99_tb_behav
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "cont99_tb_behav -key {Behavioral:sim_1:Functional:cont99_tb} -tclbatch {cont99_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.2
Time resolution is 1 ps
source cont99_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'cont99_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
restart
INFO: [Simtcl 6-17] Simulation restarted
run all
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
run: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 5835.176 ; gain = 0.000 ; free physical = 65 ; free virtual = 7866
INFO: [Common 17-344] 'run' was cancelled
add_wave {{/cont99_tb/uut/u1/fincuenta}} 
restart
INFO: [Simtcl 6-17] Simulation restarted
run all
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
run: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 5835.176 ; gain = 0.000 ; free physical = 104 ; free virtual = 7855
INFO: [Common 17-344] 'run' was cancelled
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'cont99_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE' step in '/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav'
xvlog -m64 --relax -prj cont99_tb_vlog.prj
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bcd1contador
INFO: [VRFC 10-311] analyzing module cont99
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sim_1/new/cont99_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module cont99_tb
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav'
Vivado Simulator 2015.2
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: /share2/Xilinx/Vivado/2015.2/bin/unwrapped/lnx64.o/xelab -wto c7af4f02b1ba478697011b7527df2967 --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot cont99_tb_behav xil_defaultlib.cont99_tb xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port ce [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v:32]
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 27. Module cont99 doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 1. Module bcd1contador doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 1. Module bcd1contador doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 27. Module cont99 doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 1. Module bcd1contador doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" Line 1. Module bcd1contador doesn't have a timescale but at least one module in design has a timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
WARNING: [XSIM 43-3447] Restricting number of parallel compilation jobs to 4 to avoid system resource limitations.
Compiling module xil_defaultlib.bcd1contador
Compiling module xil_defaultlib.cont99
Compiling module xil_defaultlib.cont99_tb
Compiling module xil_defaultlib.glbl
Built simulation snapshot cont99_tb_behav
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "cont99_tb_behav -key {Behavioral:sim_1:Functional:cont99_tb} -tclbatch {cont99_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2015.2
Time resolution is 1 ps
source cont99_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'cont99_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
ERROR: [Vivado 12-106] *** Exception: java.lang.ClassCastException: sun.awt.image.BufImgSurfaceData cannot be cast to sun.java2d.xr.XRSurfaceData (See /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado_pid1284.debug)
exit
INFO: [Common 17-206] Exiting Vivado at Tue Oct 20 08:30:53 2015...