#-----------------------------------------------------------
# Vivado v2015.2 (64-bit)
# SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
# IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
# Start of session at: Tue Oct 20 10:07:39 2015
# Process ID: 13223
# Log file: /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado.log
# Journal file: /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/share2/Xilinx/Vivado/2015.2/data/ip'.
open_project: Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 5717.316 ; gain = 78.703 ; free physical = 972 ; free virtual = 9511
import_files -norecurse /home/leon/Dc2015/EI1060/sourceverilog/simples/mult/multcsaseg.v
update_compile_order -fileset sources_1
import_files -norecurse /home/leon/Dc2015/EI1060/sourceverilog/simples/mult/multcsa.v
update_compile_order -fileset sources_1
import_files -norecurse /home/leon/Dc2015/EI1060/sourceverilog/simples/mult/csan.v
update_compile_order -fileset sources_1
reset_run synth_1
launch_runs synth_1
INFO: [HDL 9-2216] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/new/alarma.v" into library work [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/new/alarma.v:1]
INFO: [HDL 9-2216] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v" into library work [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/examen/conta99.v:1]
INFO: [HDL 9-2216] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/mult/csan.v" into library work [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/mult/csan.v:1]
INFO: [HDL 9-2216] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/mult/multcsa.v" into library work [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/mult/multcsa.v:1]
INFO: [HDL 9-2216] Analyzing Verilog file "/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/mult/multcsaseg.v" into library work [/home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.srcs/sources_1/imports/mult/multcsaseg.v:1]
[Tue Oct 20 10:18:39 2015] Launched synth_1...
Run output will be captured here: /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.runs/synth_1/runme.log
launch_runs impl_1
[Tue Oct 20 10:19:14 2015] Launched impl_1...
Run output will be captured here: /home/leon/Dc2015/EI1060/sourceverilog/simples/examen/project_1/project_1.runs/impl_1/runme.log