module Vrexcess3 ( CLK, CLR_L, LD_L, ENP, ENT, D, Q, RCO );
  input CLK, CLR_L, LD_L, ENP, ENT;
  input [3:0] D;
  output [3:0] Q;
  output RCO;
  reg [3:0] Q;
  reg RCO; 

  always @ (posedge CLK)  // Create the counter f-f behavior
    if (!CLR_L)                           Q <= 4'd3;
    else if (!LD_L)                       Q <= D;
    else if (ENT && ENP && (Q == 4'd12))  Q <= 4'd3;
    else if (ENT && ENP)                  Q <= Q + 1;
    else                                  Q <= Q;

  always @ (Q or ENT)     // Create RCO combinational output
    if (ENT && (Q == 4'd12))              RCO = 1;
    else                                  RCO = 0;
endmodule