module Vr74x169 ( CLK, CLR_L, LD_L, ENP_L, ENT_L, UPDN, D, Q, RCO_L );
  input CLK, CLR_L, LD_L, ENP_L, ENT_L, UPDN;
  input [3:0] D;
  output [3:0] Q;
  output RCO_L;
  reg [3:0] Q;
  reg RCO_L;

  always @ (posedge CLK)        // Create the counter f-f behavior
    if (!CLR_L )                               Q <= 4'b0;
    else if (!LD_L)                            Q <= D;
    else if (!ENT_L && !ENP_L &&  UPDN)        Q <= Q + 1;
    else if (!ENT_L && !ENP_L && !UPDN)        Q <= Q - 1;
    else                                       Q <= Q;

  always @ (Q or ENT_L or UPDN) // Create RCO_L combinational output
    if      (!ENT_L &&  UPDN && (Q == 4'd15))  RCO_L = 0;
    else if (!ENT_L && !UPDN && (Q == 4'd0 ))  RCO_L = 0;
    else                                       RCO_L = 1;
endmodule