`include "C:/Xilinx/verilog/src/ISE/unisim_comp.v"
module VrSMexs( CLOCK, RESET, A, B, Z );
  input CLOCK, RESET, A, B;
  output Z;
  wire Z;             // declared as wire for continuous assignment
  wire LASTA;         // LASTA holds last value of A
  reg [1:0] Snext;    // Next state
  wire [1:0] Sreg;    // State register
  parameter [1:0] INIT    = 2'b00,  // Define the states
                  LOOKING = 2'b10,
                  OK      = 2'b11;

  FDR U1 (.C(CLOCK), .R(RESET), .D(Snext[0]), .Q(Sreg[0]) );  
  FDR U2 (.C(CLOCK), .R(RESET), .D(Snext[1]), .Q(Sreg[1]) );  
  FD  U3 (.C(CLOCK), .D(A), .Q(LASTA) );  

  always @ (A, B, LASTA, Sreg) begin // Next-state logic
    case (Sreg)
      INIT:    Snext = LOOKING;
      LOOKING: if (A==LASTA)         Snext = OK;
               else                  Snext = LOOKING;
      OK:      if (B==1 || A==LASTA) Snext = OK;
               else                  Snext = LOOKING;
      default                        Snext = INIT;
    endcase
  end

  assign Z = (Sreg==OK) ? 1 : 0;     // Output logic
endmodule