module VrSMexp( CLOCK, RESET, A, B, Z );
  input CLOCK, RESET, A, B;
  output Z;
  reg Z, Zn;
  reg [2:0] Sreg, Snext;          // State register and next state
  parameter [2:0] INIT = 3'b000,  // Define the states
                  A0   = 3'b001,
                  A1   = 3'b010,
                  OK0  = 3'b011,
                  OK1  = 3'b100;

  always @ (posedge CLOCK) begin  // Create state and output memory
    if (RESET==1) Sreg <= INIT; else Sreg <= Snext;
    Z <= Zn;
  end

  always @ (A, B, Sreg) begin  // Next-state logic
    case (Sreg)
      INIT:   if (A==0)  Snext = A0;
              else       Snext = A1;
      A0:     if (A==0)  Snext = OK0;
              else       Snext = A1;
      A1:     if (A==0)  Snext = A0;
              else       Snext = OK1;
      OK0:    if (A==0)  Snext = OK0;
              else if ((A==1) && (B==0)) Snext = A1;
              else                       Snext = OK1;
      OK1:    if ((A==0) && (B==0))      Snext = A0;
              else if ((A==0) && (B==1)) Snext = OK0;
              else                       Snext = OK1;
      default Snext = INIT;
    endcase
  end

  always @ (Snext)        // Output logic
    case (Snext)
      INIT, A0, A1: Zn = 0;
      OK0, OK1:     Zn = 1;
      default       Zn = 0;
    endcase
endmodule