module VrSMexa( CLOCK, RESET, A, B, Z );
  input CLOCK, RESET, A, B;
  output Z;
  wire Z;              // declared as wire for continuous assignment
  reg LASTA;                        // LASTA holds last value of A
  reg [1:0] Sreg, Snext;            // State register and next state
  parameter [1:0] INIT    = 2'b00,  // Define the states
                  LOOKING = 2'b10,
                  OK      = 2'b11;

  always @ (posedge CLOCK) begin     // State memory (w/ sync reset)
    if (RESET==1) Sreg <= INIT; else Sreg <= Snext;
    LASTA <= A;
  end

  always @ (A, B, LASTA, Sreg) begin // Next-state logic
    case (Sreg)
      INIT:    Snext = LOOKING;
      LOOKING: if (A==LASTA)         Snext = OK;
               else                  Snext = LOOKING;
      OK:      if (B==1 || A==LASTA) Snext = OK;
               else                  Snext = LOOKING;
      default                        Snext = INIT;
    endcase
  end

  assign Z = (Sreg==OK) ? 1 : 0;     // Output logic
endmodule