// Handel-C decade counter and test - for the Altera NIOS board void increment_decade(unsigned 4 *count, unsigned 1 Hold); unsigned 8 sevenseg(unsigned 4 bcd); set clock = external "L6" with { rate = 33 }; // 33.333 MHz void main (void) { // Declarations unsigned 1 stop; unsigned 4 count[2]; unsigned 1 hold; unsigned 24 cycles; unsigned 8 seg1, seg2; // Hardware interface // Seven segment display 1 interface bus_out () display1 (unsigned 8 out = seg1) with { data = {"D18", "V17", "V18", "Y17", "V8", "Y7", "U11", "R11"} }; // Seven segment display 2 interface bus_out () display2 (unsigned 8 out = seg2) with { data = {"C18", "W17", "U18", "Y18", "W18", "U8", "T11", "R10"} }; // Initialisation par { stop = 0; count[0] = 0; count[1] = 0; } par { // Cycle counter - use this to divide the clock while (!stop) par { cycles++; hold = (cycles != 0xffffff); } // Call the counter while (!stop) increment_decade(count, hold); // Seven segment displays (active low) - musn't call these in parallel! while (!stop) { seg1 = sevenseg(count[1]); seg2 = sevenseg(count[0]); } } } // This function describes a two digit BCD counter void increment_decade(unsigned 4 *count, unsigned 1 Hold) { if (Hold) count[0] = count[0]; /* You have to do something! */ else if ( count[0] == 9 ) par { /* "par" ensures one cycle */ count[0] = 0; if ( count[1] == 9 ) count[1] = 0; else count[1]++; } else count[0]++; } // This function describes a BCD to seven-segment encoder. // The display inputs are active low. At 33 MHz, it doesn't matter // that this takes two clocks to execute. unsigned 8 sevenseg(unsigned 4 bcd) { unsigned 8 seg; switch (bcd) { case 0: seg = 0b11000000; break; case 1: seg = 0b11111001; break; case 2: seg = 0b10100100; break; case 3: seg = 0b10110000; break; case 4: seg = 0b10011001; break; case 5: seg = 0b10010010; break; case 6: seg = 0b10000011; break; case 7: seg = 0b11111000; break; case 8: seg = 0b10000000; break; case 9: seg = 0b10011000; break; default: seg = 0b01110111; break; } return seg; }