// Top-level of serial/parallel with Altera PLL


// Xilinx DLL - clock divider
signal unsigned 1 sclk, pclk;

// Clock pin
interface port_in (unsigned 1 clk) pi_serial_clock ();

// Instance of Xilinx IBUFG clock input
interface IBUFG (unsigned 1 O) myIBUFG (unsigned 1 I = pi_serial_clock.clk);

// Instance of Xilinx BUFG global buffer for feedback clock
interface BUFG  (unsigned 1 O with { clockport = 1} ) myBUFGFB (unsigned 1 I = sclk);

// Instance of Xilinx CLKDLL, configured for divide by 8
interface
	CLKDLL (
		unsigned 1 CLK0,
		unsigned 1 CLK90,
		unsigned 1 CLK180,
		unsigned 1 CLK270,
		unsigned 1 CLK2X,
		unsigned 1 CLKDV,
		unsigned 1 LOCKED
	)
	myCLKDLL (
		unsigned 1 CLKIN = myIBUFG.O,
		unsigned 1 CLKFB = myBUFGFB.O,
		unsigned 1 RST = 0
	) with { properties = { {"CLKDV_DIVIDE","8"} } } ;

// Instance of Xilinx BUFG global buffer for internal (divided) clock
interface BUFG  (unsigned 1 O with { clockport = 1 } ) myBUFGDV
                (unsigned 1 I = myCLKDLL.CLKDV);

set clock = internal myBUFGDV.O;

interface xilinx () fifo_inst (unsigned 1 sclk = sclk, unsigned 1 pclk = pclk);

void main (void)
{
	sclk = myCLKDLL.CLK0;
	pclk = myBUFGDV.O;

}