// Top-level of serial/parallel with Altera PLL


// Altera PLL - clock divider; Generate the divby8 module using
// the Altera MegaWizard.

signal unsigned 1 serial_clock, sclk, pclk;

interface divby8 (unsigned 1 clock0 with {clockport=1},
                  unsigned 1 clock1 with {clockport=1}
				 ) pll (unsigned 1 inclock = serial_clock);

interface bus_in (unsigned 1) bi_serial_clock ();

interface fifo () fifo_inst (unsigned 1 sclk = sclk, unsigned 1 pclk = pclk);

set clock = internal pll.clock1;

void main (void)
{
	serial_clock = bi_serial_clock.in;
	sclk = pll.clock0;
	pclk = pll.clock1;

}