// Use a dual port memory for serial - parallel conversion across
// two clock domains.

// The serial block uses the external fast clock

interface port_in (unsigned 1 sclk) pi_sclk ();
set clock = internal pi_sclk.sclk;

// Declaration of type dpram and memory to store data
// (Definition is in the file parallel.hcc)

extern mpram dpram
{
	wom unsigned 8 memwrite[256];
	rom unsigned 8 memread[256];
} mem;

#ifdef SIMULATE

extern "C" int printf(const char *fmt, ...);

void write(unsigned 8);

extern unsigned 1 Read_data;

#endif

// Input regs
unsigned 1 Data_in, Start;

// Stop simulation
unsigned 1 stop;

void main (void)
{

#ifndef SIMULATE

	unsigned 1 parallel_clock;

	// FPGA pins
	interface bus_in (unsigned 1) bi_data_in ();
	interface bus_in (unsigned 1) bi_data_start ();
	
#endif

	// Shift register
	unsigned 8 SR;

	// Next free address
	unsigned 8 next;

	// Initialise
	next = 0;
	stop = 0;

	par {

#ifdef SIMULATE

		// Test stimulus
		seq {

			write(0x01);
			write(0x02);
			write(0x03);
			write(0x04);
			write(0x05);
			write(0x06);
			write(0x07);
			write(0x08);
			stop = 1;
		}

#endif

		while (!stop) par {

#ifndef SIMULATE

			// Get inputs
			Start = bi_data_start.in;
			Data_in = bi_data_in.in;
#endif
			// Shift serial data into SR
			SR = Data_in @ SR[7:1];
		}

		// Load word into FIFO
		while (!stop) {
			if ( Start ) {
				mem.memwrite[next] = SR;
				next++;
			}
		}

	}	

}

#ifdef SIMULATE

void write ( unsigned 8 data )
{
	par {
		seq {
			Start = 1;
			Start = 0;
		}
		seq {
			Data_in = data[0];
			Data_in = data[1];
			Data_in = data[2];
			Data_in = data[3];
			Data_in = data[4];
			Data_in = data[5];
			Data_in = data[6];
			Data_in = data[7];
		}
	}
}

#endif