`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:08:11 04/07/2014
// Design Name:   pruebas_int
// Module Name:   /home/leon/Dc2014/EE1037/PRACTICAS/cript/xil/aes/tb_prueba-int.v
// Project Name:  aes
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: pruebas_int
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////


module tb_prueba_int;

	// Inputs
	reg clk;
	reg rst;
	reg [7:0] swt;

	// Outputs
	wire [3:0] leds;
	wire [6:0] ssg;
	wire [3:0] an;

estimulos_spi estimulos (
	 .sdo(sdi),
    .ssg(ssg), 
    .an(an), 
    .sdi(sdo), 
    .sclk(sclk), 
    .mclk(clk), 
    .rst(rst), 
    .ce(ce)
    );
// Instantiate the module
spibas spibas (
    .ce(ce), 
    .sclk_pri(sclk), 
    .clk(clk), 
    .sdi_pri(sdi), 
    .sdo(sdo), 
    .rst(rst), 
    .leds(leds), 
//    .ssg(ssg), 
//    .an(an), 
    .swt(swt)
    );
always #5 clk=~clk;
	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 1;
		swt = 8'hC5;
		// Wait 100 ns for global reset to finish
		#10000;
        rst=0;
		  #100000;
		// Add stimulus here

	end
      
endmodule