`timescale 1ns / 1ns

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:38:29 11/20/2013
// Design Name:   keyboard
// Module Name:   C:/key/tv.v
// Project Name:  S3demo
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: keyboard
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tf_kb2display (CLK);

	// Inputs
	output reg CLK;
	reg RST;
	reg kd;
	reg kc;

	// Outputs
	wire [3:0] an;
	wire [6:0] ssg;
	reg [11:0] dato;
	reg [6:0] segmentos [4:0];
	
	
	localparam CICLO=104000;
	always @(posedge(CLK)) begin: alm
   integer idx;
	idx=((an==7)?0:((an==11)?1:((an==13)?2:(an==14)?3:4)));
   segmentos[idx]=ssg;
   end
	// Instantiate the Unit Under Test (UUT)
	kb2display uut (
		.CLK(CLK), 
		.RST(RST), 
		.kd(kd), 
		.kc(kc), 
		.an(an), 
		.ssg(ssg)
	);

always begin #12 CLK=1;#8 CLK=0; end


	initial begin: TB
	   integer i;
		$dumpfile("kb2display.vcd");
		$dumpvars(0,tf_kb2display);
		dato=11'b10111100000;//codigo F0
		// Initialize Inputs
		for (i=0;i<16;i=i+1) segmentos[i]=0;
		RST = 1;
		kd = 0;
		kc = 0;
		// Wait 100 ns for global reset to finish
		#100;
		RST=0;
		#100;
		for (i=0;i<11;i=i+1)
		begin
		kc=1;
		#50
		kd=dato[0];
		#50
		kc=0;
		#50
		dato=dato >> 1;
		end
		dato=11'b11000111000;//Tecla A codigo 1C
		for (i=0;i<11;i=i+1)
		begin
		kc=1;
		#50
		kd=dato[0];
		#50
		kc=0;
		#50
		dato=dato >> 1;
		end
		kc=1;
		#50;
		#680000
		
		  $write ("SEG %b-AN %h \n",segmentos[3],4'h3);
		  $write ("SEG %b-AN %h \n",segmentos[2],4'h2);
		  $write ("SEG %b-AN %h \n",segmentos[1],4'h1);
		   $write ("SEG %b-AN %h \n",segmentos[0],4'h0);
		 #50
	  $stop(1);

end
		// La salida tiene ser parecido (puede tener otro orden o correspondencia 
		//los segmenttos con los anodos:
		// an=4'b1100,ssg[6:0]=6'b1111001 - 1
		// an=4'b1101,ssg[6:0]=6'b1000110 - C
		// an=4'b1011,ssg[6:0]=6'b0011001 - 4
		// an=4'b0111,ssg[6:0]=6'b1111001 - 1
		
  
endmodule